SystemVerilog教程之Data Types Part-I

Introduction

SystemVerilog在Verilog的基础上添加了许多新数据类型,以提高仿真器的内存利用率。

Integer

数据类型可以分为2-state类型和** 4-state类型**。 2-state类型只能是0、1,而4-state类型可以是0、1、X和Z。
与 4-state类型相比,2-state类型消耗更少(50%)的内存,仿真速度更快。

2-state类型是:

shortint: 16-bit signed integer.
int :32-bit signed integer.
longint :64-bit signed integer.
byte :8-bit signed integer, can be used for storing ASCII charater.
bit :User defined vector types.

4-state类型是:

logic :User defined vector types.
reg :User defined vector types.
wire :User defined vector types.
integer :32-bit signed integer.
time :64-bit unsigned integer.

integer类型可以是有符号无符号的,在声明需要足够仔细,因为有符号数和无符号数的运算结果不一样。

默认情况下,byte,shortint,int,integer和longint是有符号数,bit,reg,logic和wire是无符号数。

示例:

module data_types();module data_types();
 
bit      data_1bit;
byte     data_8bit;
shortint data_16bit;
int      data_32bit;
longint  data_64bit;
integer  data_integer;
 
bit      unsigned data_1bit_unsigned;
byte     unsigned data_8bit_unsigned;
shortint unsigned data_16bit_unsigned;
int      unsigned data_32bit_unsigned;
longint  unsigned data_64bit_unsigned;
integer  unsigned data_integer_unsigned;
 
initial begin
  data_1bit   = {32{4'b1111}};
  data_8bit   = {32{4'b1111}};
  data_16bit  = {32{4'b1111}};
  data_32bit  = {32{4'b1111}};
  data_64bit  = {32{4'b1111}};
  data_integer= {32{4'b1111}};
  $display("data_1bit    =%0d",data_1bit);
  $display("data_8bit    =%0d",data_8bit);
  $display("data_16bit   =%0d",data_16bit);
  $display("data_32bit   =%0d",data_32bit);
  $display("data_64bit   =%0d",data_64bit);
  $display("data_integer = %0d",data_integer);
  data_1bit   = {32{4'bzx01}};
  data_8bit   = {32{4'bzx01}};
  data_16bit  = {32{4'bzx01}};
  data_32bit  = {32{4'bzx01}};
  data_64bit  = {32{4'bzx01}};
   data_integer={32{4'bzx01}};
  $display("data_1bit    =%b",data_1bit);
  $display("data_8bit    =%b",data_8bit);
  $display("data_16bit   =%b",data_16bit);
  $display("data_32bit   =%b",data_32bit);
  $display("data_64bit   =%b",data_64bit);
   $display("data_integer= %b",data_integer);
  data_1bit_unsigned   ={32{4'b1111}};
  data_8bit_unsigned   ={32{4'b1111}};
  data_16bit_unsigned  ={32{4'b1111}};
  data_32bit_unsigned  ={32{4'b1111}};
  data_64bit_unsigned  ={32{4'b1111}};
  data_integer_unsigned  ={32{4'b1111}};
  $display("data_1bit_unsigned = %d",data_1bit_unsigned);
  $display("data_8bit_unsigned = %d",data_8bit_unsigned);
  $display("data_16bit_unsigned = %d",data_16bit_unsigned);
  $display("data_32bit_unsigned = %d",data_32bit_unsigned);
  $display("data_64bit_unsigned = %d",data_64bit_unsigned);
  $display("data_integer_unsigned = %d",data_integer_unsigned);
  data_1bit_unsigned   ={32{4'bzx01}};
  data_8bit_unsigned   ={32{4'bzx01}};
  data_16bit_unsigned  = {32{4'bzx01}};
  data_32bit_unsigned  ={32{4'bzx01}};
  data_64bit_unsigned  ={32{4'bzx01}};
  data_integer_unsigned  ={32{4'bzx01}};
  $display("data_1bit_unsigned = %b",data_1bit_unsigned);
   $display("data_8bit_unsigned  = %b",data_8bit_unsigned);
  $display("data_16bit_unsigned = %b",data_16bit_unsigned);
  $display("data_32bit_unsigned = %b",data_32bit_unsigned);
  $display("data_64bit_unsigned = %b",data_64bit_unsigned);
  $display("data_integer_unsigned = %b",data_integer_unsigned);
   #1$finish;
end
 
endmodule

Simulation Output

data_1bit    = 1 
data_8bit    = -1 
data_16bit   = -1
data_32bit   = -1
data_64bit   = -1 
data_integer = -1 

data_1bit    = 1 
data_8bit    = 00010001 
data_16bit   = 0001000100010001 
data_32bit   = 00010001000100010001000100010001 
data_64bit   = 0001000100010001000100010001000    100010001000100010001000100010001 
data_integer = zx01zx01zx01zx01zx01zx01zx01zx01 

data_1bit_unsigned  = 1 
data_8bit_unsigned  = 255 
data_16bit_unsigned = 65535
 data_32bit_unsigned = 4294967295 
 data_64bit_unsigned = 18446744073709551615 
 data_integer_unsigned = 4294967295 
 
 data_1bit_unsigned  = 1 
 data_8bit_unsigned  = 00010001 
 data_16bit_unsigned = 0001000100010001
  data_32bit_unsigned = 00010001000100010001000100010001 
  data_64bit_unsigned = 0001000100010001000100010001000 100010001000100010001000100010001 
    data_integer_unsigned = zx01zx01zx01zx01zx01zx01zx01zx01

string

string数据类型用于存储字符串,其大小是动态的。
string数据类型还带有很多内置方法。

Str1 ==Str2
检查两个字符串是否相等。如果它们相等则返回1,如果不相等则返回0。

Str1!= Str2
检查两个字符串是否不相等。

{STR1,STR2,…,Strn }
连接字符串,其类型为string。

{multiplier{Str}}
复制。乘数必须是整数类型,其返回值是N个字符串。

Str.method(…)
.运算符用于在字符串上调用指定的方法。

Str[index]
索引。返回给定索引处的一个字节。索引的范围从0到N-1,其中N是字符串中的字符数。如果索引超出范围,则返回0。

本文转载自公众号:芯片数字实验室
原文链接:https://mp.weixin.qq.com/s/ExPw1OSIzYT15B1dGEZzfg
未经作者同意,请勿转载!

推荐阅读

  • SystemVerilog教程之Verilog Basics Part-II
  • SystemVerilog教程之Verilog Basics Part-III

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